• Features

Features

• High lighting Verilog reserved words "module", "input", "begin", "wire", "task", "function" etc.
• Coloring comment Eclipse Verilog Editor supports two type of comment of Verilog language.
  • // single line comment

    multi-line comment

• Go to matching bracket Eclipse Verilog Editor recognizes "[]", "{}", "()", "begin/end" and "fork/join" as bracket.
• Contents outline view The outline view shows module definition, module instantiation, task, function and comment with valid sentence in a Verilog source code.
  • The version 0.1.1 fixed some bugs of source code parsing.
• Code template begin/end pair, always/initial block, function and task
• Open declaration Go to module declaration of selected word by searching a project hierarchy.
  • It is valid when you defined a same module name with file name, e.g. module "adder" is defined in file "adder.v".
• Automatic port connection for instantiation When you enter module name only, Eclipse Verilog Editor completes module instantiation code with named port connection.
  • e.g. If you have already defined adder.v:

  • module adder( a, b, sum );
    parameter WIDTH = 16;
    input[WIDTH-1:0] a, b ;
    output[WIDTH-1:0] sum ;
    ...
    endmodule

    • You can instantiate this.

    adder #(
      .WIDTH(16)
    )
      adder(
      .clk(clk),
      .a(a),
      .b(b),
      .sum(sum)
    );

  It is more effective when you are using more complicated modules. If you don't need Verilog-2001 style parameter, you can disable it in the preference page.
• Content assist Content Assist completes a whole phrase which you want. Eclipse provides a proposal list. The proposal list may include code templates, signals and module instances. But it depend on Verilog context. Now there are three contexts.
• outside module
  1. inside module, but outside statement
  2. inside statement
  There are always no proposals in 1. The proposals in 2 includes some templates and module instances. The proposal in 3 includes "begin/end" template and signals, which defined in same module.
• Module Hierarchy Eclipse Verilog Editor provides "Hierarch" view.
  • The Module Hierarchy view shows module(s) defined in current editor page at first. You can click "+" and expand hierarchical tree of module instantiation. You can copy hierarchical view as text to clipboard. So you can paste it to any other text editors.
• Problems view Eclipse Verilog Editor provides "Problems" view.

  • The Problems view shows compiler error and warning messages. The compiler is out of Eclipse. Now you can use [http://icarus.com/eda/verilog/ Icarus Verilog], [http://www.pragmatic-c.com/gpl-cver/index.htm CVer] or [http://www.freehdl.seul.org/ FreeHDL]..

• VHDL support VHDL language is supported. All Verilog features are supported.
• Preference page It can modify colors and font styles in editor and command line option for external Verilog compiler.
• Code Formatter (beta) Code formatter arranges Verilog source code just like same function with JDT. It corrects indent and space characters before/after operators.
  • Now you are forced to my own code style because there are no preference page of Verilog code style. Please report your required preference of code style. Of course welcome to bug report with your expected code too. Code formatter can do on Verilog language only now. Please contribute about VHDL.
• Console view Console view show output messages from external compiler and error messages from internal code parser. It make you easy to fix problems.
• Verilog/VHDL Perspective Verilog/VHDL Perspective provides customized arrangement about views alignment and new wizard.
• New wizard New Verilog module, new VHDL entity and new Verilog/VHDL project wizard are supported.
• Simulator builder

  Verilog/VHDL project supports simulator builder, which can launch external circuit simulators, then parse error messages and reflect problems view from them. Now [http://icarus.com/eda/verilog/ Icarus Verilog], [http://www.pragmatic-c.com/gpl-cver/index.htm CVer] and [http://www.freehdl.seul.org/ FreeHDL] are supported. And other compiler can be supported, using custom error parser.

• Custom error parser Custom error parser can support any complier error message. It match pattern with user defined regular expressions.
• Log viewer Log viewer reads the compiler log files, then parse and update problems view. So you can launch simulator outside Eclipse and reflect problems view. Log viewer opens *.log files by default. You can also change file associations.
• Text hover When the mouse pointer is on any signals, the text hover show a declaration line of the signal.
• Block Comment and Block Uncomment JDT style block comment and uncomment are supported. The default key assigns are Ctrl+Shift+/ and Ctrl+Shift+\.
• Custom code template JDT style code template are supported. The template pattern can be defined by user